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VLSI

SNO

LOW POWER

ETVLSI1 A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging
ETVLSI2 Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture
ETVLSI3 Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
ETVLSI4 A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption
ETVLSI5 Resource-Efficient SRAM-based Ternary Content Addressable Memory
ETVLSI6  Write-Amount-Aware Management Policies for STT-RAM Caches
ETVLSI7  Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA
ETVLSI8 High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder
ETVLSI9 High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
ETVLSI10 Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
ETVLSI11 Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map
ETVLSI12 Efficient Designs of Multi-ported Memory on FPGA
ETVLSI13 High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
ETVLSI14 An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock
ETVLSI15 A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique
ETVLSI16 Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares
ETVLSI17 Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm
ETVLSI18 A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission
ETVLSI19 Scalable Device Array for Statistical Characterization of BTI-Related Parameters
ETVLSI20 AREA EFFICIENT/ TIMING & DELAY REDUCTION
ETVLSI21 VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding
ETVLSI22 ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware
ETVLSI23 Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs
ETVLSI24 Efficient Soft Cancelation Decoder Architectures for Polar Codes
ETVLSI25 Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition
ETVLSI26 Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication
ETVLSI27 FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers over GF (2m) and Their Applications in Trinomial Multipliers
ETVLSI28 Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields
ETVLSI29 Antiwear Leveling Design for SSDs With Hybrid ECC Capability
ETVLSI30 Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems

Audio, Image and Video Processing

ETVLSI31 A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding
ETVLSI32 RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
ETVLSI33  Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations
ETVLSI34 Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
ETVLSI35 An FPGA-Based Hardware Accelerator for Traffic Sign Detection
ETVLSI36 Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations
ETVLSI37 Time-Encoded Values for Highly Efficient Stochastic Circuits
ETVLSI38 Design of Power and Area Efficient Approximate Multipliers

VERIFICATION

ETVLSI39  COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits
ETVLSI40  Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction

NETWORKING

ETVLSI41 Multicast-Aware High-Performance Wireless Network-on-Chip Architectures
ETVLSI42 VLSI – BACK END PROJECT – TANNER(nm) / HSPICE(nm) / DSCH3 – MICROWIND(um)
ETVLSI43 Temporarily Fine-Grained Sleep Technique for Near- and Sub-threshold Parallel Architectures
ETVLSI44 Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique
ETVLSI45 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
ETVLSI46 Delay Analysis for Current Mode Threshold Logic Gate Designs
ETVLSI47 Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
ETVLSI48 Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating
ETVLSI49 A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications
ETVLSI50 A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS
ETVLSI51 Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application
ETVLSI52 An All-MOSFET Sub-1-V Voltage Reference With a−51-dB PSR up to 60 MHz
ETVLSI53 A 65-nm CMOS Constant Current Source with Reduced PVT Variation
ETVLSI54 A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy
ETVLSI55 Preweighted Linearized VCO Analog-to-Digital Converter
ETVLSI56 A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression
ETVLSI57 Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template
ETVLSI58 On Micro-architectural Mechanisms for Cache Wear out Reduction
ETVLSI59 Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology
ETVLSI60 A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing
ETVLSI61 A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures